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74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs
October 1993 Revised January 1999
74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16543 16-bit transceiver contains two sets of Dtype latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Each byte has separate control inputs, which can be shorted together for full 16-bit operation.
Features
s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 32 mA and current sinking capability of 64 mA s Separate control logic for each byte s 16-bit version of the ABT543 s Separate controls for data flow in each direction s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:
Order Number 74ABT16543CSSC 74ABT16543CMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A0-A15 Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B0-B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS011646.prf
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74ABT16543
Logic Symbol
Data I/O Control Table
Inputs CEABn LEABn OEABn H X L X L X H L X X X X X H L Latch Status Output Buffers (Byte n) Latched Latched Transparent -- -- (Byte n) HIGH Z -- -- HIGH Z Driving
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
Functional Description
The ABT16543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be low in order to enter data from the A port or take data from the B-Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate control inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver.
Logic Diagrams
Byte 1 (0:7) Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT16543
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to +5.5V -0.5V to VCC -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -65C to +150C -55C to +125C -55C to +150C
DC Latchup Source Current Over Voltage Latchup (I/O)
-500 mA 10V
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns -40C to +85C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current -1 -1 IIH + IOZH Output Leakage Current IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Output Leakage Current -100 10 -10 -275 50 100 1.0 60 1.0 2.5 No Load 0.25 mA/MHz Max A A mA A A mA mA mA mA A Max VIN = 0.5V (Non-I/O Pins) (Note 3) VIN = 0.0V (Non-I/O Pins) 0V-5.5V VOUT = 2.7V (An, Bn); OEAB or CEAB = 2V 0V-5.5V VOUT = 0.5V (An, Bn); OEAB or CEAB = 2V Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 3) Max Max 0.0V Max Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE All Others at VCC or GND VI = VCC - 2.1V All Others at VCC or GND Outputs Open, CEAB, OEAB, LEAB = GND, CEBA = VCC, One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed but not tested.
Min 2.0
Typ
Max
Units V
VCC
Conditions Recognized HIGH Signal Recognized LOW Signal
0.8 -1.2 2.5 2.0 0.55 4.75 1 1 7 100
V V Min
IIN = -18 mA (Non I/O Pins) IOH = -3 mA, (An, Bn) IOH = -32 mA, (An, Bn)
V V A A A
Min 0.0 Max Max Max
IOL = 64 mA, (A n, Bn) IID = 1.9 A, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) ((Note 3) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn)
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74ABT16543
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay An to Bn or Bn to An Propagation Delay LEABn to Bn, LEBAn to An Enable Time OEBAn or OEABn to An or Bn Disable Time OEABn or OEBAn to An or Bn Enable Time CEBAn or CEABn to An or Bn Disable Time CEBAn or CEABn to An or Bn 1.7 3.2 6.3 1.7 6.3 ns 1.5 3.1 6.2 1.5 6.2 ns 1.6 3.1 6.0 1.6 6.0 ns 1.5 2.8 5.2 1.5 5.2 ns 1.5 3.0 5.5 1.5 5.5 ns 1.5 VCC = +5.0V CL = 50 pF Typ 3.0 Max 5.7 1.5 TA = -55C to +85C VCC = 4.5V-5.5V CL = 50 pF Min Max 5.7 ns Units
AC Operating Requirements
(SSOP Package) TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(L) Setup Time, HIGH or LOW An or Bn to LEBAn or LEABn Hold Time, HIGH or LOW An or Bn to LEBAn or LEABn Pulse Width, LOW 2.0 2.0 1.0 1.0 3.0 Max Min 2.0 2.0 1.0 1.0 3.0 ns ns TA = -55C to +85C VCC = 4.5V-5.5V CL = 50 pF Max ns Units
Capacitance
Symbol CIN CI/O (Note 4) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF Conditions TA = 25C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn)
Note 4: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT16543
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns
FIGURE 2. VM = 1.5V
tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT16543
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74ABT16543 16-Bit Registered Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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